M16 = NAND(NAND(Q0,Q1),NAND(Q2,M16))įurther testing has indicated that the internal products (Q0 NAND Q1, Q2 NAND M16) are brought out to test pads for factory verification.
(Below, we call the latched form of D0→Q0, D1→Q1, and D2→Q2). The latch, just like in the discrete logic mappers that use it, latches the bottom 3 bits of the data bus when it is written to. It is very likely that the support hardware is a 74HC161 latch and a 74HC00 quad NAND gate, based on the specific order that the traces enter the epoxy blob. Since this pak was only ever released with epoxy covering wirebonded silicon dice, the following is guesswork: Despite that the MMC3 thinks this register is RAM, the register itself does not, so it is not readable and attempting to read it will return open bus. └──── the MMC3's PRG A16 is ANDed with this bit before going to PRG ROM.Īdditionally connected to A17 on both PRG and CHR ROM.Īs far as the MMC3 is concerned, this is the PRG-RAM, so you will need to enable writes to PRG-RAM to update it. │└┴── If 3, forces PRG A16 high regardless of Q bit otherwise The Outer Bank Select register is cleared by the CIC reset line, so if this multicart is used in a console without a functioning lockout chip, only a full power cycle will get back to the menu. This game, like Super Spike V'Ball + Nintendo World Cup, replaces PRG RAM with a single register to enforce multiple "jail cells" containing each game.
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